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ADuC7060
Table 108. GPxCON MMR Bit Descriptions
Table 112. GPxSET MMR Bit Descriptions
Bit
31:30
29:28
27:26
25:24
23:22
21:20
19:18
Description
Reserved.
Reserved.
Reserved.
Selects the function of the P0.6/RTS and P1.6/PWM pins.
Reserved.
Selects the function of the P0.5/CTS and P1.5/PWM3 pins.
Reserved.
Bit
31:24
23:16
15:0
Description
Reserved.
Data Port x set bit.
Set to 1 by user to set bit on Port x; also sets the
corresponding bit in the GPxDAT MMR.
Cleared to 0 by user; does not affect the data output.
Reserved.
17:16
15:14
13:12
Selects the function of the P0.4/IRQ0/PWM1 and
P1.4/PWM2 pins.
Reserved.
Selects the function of the P0.3/MOSI/SDA and P1.3/TRIP
GP x CLR REGISTERS
GPxCLR are data clear Port x registers.
Table 113. GPxCLR Registers
pins.
Name
Address
Default Value
Access
11:10
9:8
7:6
Reserved.
Selects the function of the P0.2/MISO and P1.2/SYNC pins.
Reserved.
GP0CLR
GP1CLR
GP2CLR
0xFFFF0D28
0xFFFF0D38
0xFFFF0D48
0x000000XX
0x000000XX
0x000000XX
W
W
W
5:4
Selects the function of the P0.1/SCLK/SCL, P1.1/SOUT,
3:2
1:0
and P2.1/IRQ3/PWM5 pins.
Reserved.
Selects the function of the P0.0/SS, P1.0/IRQ1/SIN/T0,
GPxPAR REGISTERS
The GPxPAR registers program the parameters for Port 0, Port 1,
P2.0/IRQ2/PWM0/EXTCLK pins.
GP x DAT REGISTERS
GPxDAT are Port x configuration and data registers. They con-
and Port 2. Note that the GPxDAT MMR must always be written
after changing the GPxPAR MMR.
Table 114. GPxPAR Registers
figure the direction of the GPIO pins of Port x, set the output
value for the pins that are configured as output, and store the
input value of the pins that are configured as input.
Name
GP0PAR
GP1PAR
GP2PAR
Address
0xFFFF0D2C
0xFFFF0D3C
0xFFFF0D4C
Default Value
0x00000000
0x00000000
0x00000000
Access
R/W
R/W
R/W
Table 109. GPxDAT Registers
Name
Address
Default Value
Access
Table 115. GPxPAR MMR Bit Descriptions
GP0DAT
GP1DAT
GP2DAT
0xFFFF0D20
0xFFFF0D30
0xFFFF0D40
0x000000XX
0x000000XX
0x000000XX
R/W
R/W
R/W
Bit
31:15
23:16
Name
GPL[7:0]
Description
Reserved.
General I/O port pin functionality lock
registers.
Table 110. GPxDAT MMR Bit Descriptions
GPL[7:0] = 0, normal operation.
Bit
31:24
Description
Direction of the data.
Set to 1 by user to configure the GPIO pin as an output.
Cleared to 0 by user to configure the GPIO pin as an input.
GPL[7:0] = 1, for each GPIO pin, if this bit is
set, writing to the corresponding bit in
GPxCON or GPxDAT register bit has no
effect.
23:16
15:8
7:0
Port x data output.
Reflect the state of Port x pins at reset (read only).
Port x data input (read only).
15:8
GPDS[7:0]
Drive strength configuration. This bit is
configurable.
GPDS[x] = 0, maximum source current is 2 mA.
GPDS[x] = 1, maximum source current is 4 mA.
GP x SET REGISTERS
GPxSET are data set Port x registers.
Table 111. GPxSET Registers
7:0
GPPD[7:0]
Pull-Up Disable Port x[7:0].
GPPD[x] = 0, pull-up resistor is active.
GPPD[x] = 1, pull-up resistor is disabled.
Name
GP0SET
GP1SET
GP2SET
Address
0xFFFF0D24
0xFFFF0D34
0xFFFF0D44
Default Value
0x000000XX
0x000000XX
0x000000XX
Access
W
W
W
Rev. 0 | Page 97 of 100
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